Field of the Invention
This invention relates to processing systems and, more particularly, to data transfers between peripheral systems and processing systems.
Description of the Related Art
In general, processing systems (e.g., microcontrollers) include central processing units that are increasingly capable of processing operations at a high rate (e.g., hundreds of MHz). However, the frequency of operation of peripheral devices remains relatively constant at rates lower than the frequency of operation of central processing units (e.g., less than 100 MHz). As the difference between central processing unit throughput and peripheral throughput increases, the time for a central processing unit to access peripheral data increasingly impacts actual central processing unit throughput. For example, a central processing unit having a 300 MHz clock rate accessing a peripheral having a 30 MHz clock rate and requiring a three cycle read-access time needs a minimum of 30 central processing unit clock cycles per read of the peripheral. A system may address this problem by including a dedicated input/output processor core that has performance more closely matched to the peripheral performance and is adapted for peripheral access. However, such techniques require implementation of substantial software overhead, which may be difficult for a customer to implement. As a result, although microcontroller manufacturers make resources available to improve performance, the customer may not use those resources. Accordingly, improved techniques for interfacing between a central processing unit and peripheral devices are desired.
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